1. Technical Field
The present invention is related to a through-hole electrode substrate arranged with a through-hole electrode which passes through a front surface and rear surface of a semiconductor substrate, and is also related to a method of manufacturing the through-hole electrode substrate.
2. Field of the Invention
Recently, with the high level of integration of electronic devices and progress in miniaturization, LSI chips are becoming as small as semiconductor packaging. However, high integration via a two dimensional arrangement of chips within a package is reaching its limits. Thus, in order to improve the packaging density of chips within the package it is necessary to divide the LSI chips and stack them in three dimensions. In addition, in order to increase the operation speed of the entire semiconductor package which includes stacked LSI chips, it is necessary to reduce the distance between stacked circuits.
Thus, in order to meet the demands described above, a through-hole electrode substrate arranged with a conducting part which conducts a front surface and rear surface of a substrate is proposed as an interposer between LSI chips. In this type of through-hole electrode substrate, the through-hole electrode is formed by filling the through-hole with a conducting material (Cu for example) using electroplating.
FIG. 18 is a diagram which shows one example of a through-hole electrode substrate 10 which is arranged with a silicon substrate 11, a through-hold 12 which passes through the silicon substrate 11 in the thickness direction of the substrate, an insulating layer 13 comprised of silicon dioxide SiO2 for example, formed on a top and bottom surface from an inner wall of the through-hole 12, a through-hole electrode 14 comprised of copper (Cu), gold (Au) or multilayer plating (Cu/Ni/Au) for example, which is formed within the through-hole 12, and a wiring layer 15 comprised of copper (Cu) for example, arranged on a top and bottom surface of each of these components.
The through-hole electrode substrate 10 shown in FIG. 18 is manufactured by the method described below. First, from one surface of the silicon substrate 11 a hole which does not pass completely through the substrate is formed using a method such as RIE (Reactive Ion Etching), Deep RIE, photo-etching, or wet-etching. Next, from the other surface of the silicon substrate 11, that is, the surface opposite to the one where the hole is first formed, the silicon substrate 11 is set back (thinned) using a method such as grinding and the hole passes completely through the substrate. An insulating layer 13 is formed using a method such as LPCVD (Low Pressure Chemical Vapor Disposition) on the inner surfaces of this through-hole 12 and both surfaces (top and bottom) of the silicon substrate 11. Next, after burying a conducting material comprised from a metal material such as copper (Cu) which becomes the through-hole electrode 14 within the through-hole 12 on which the insulating film 13 is formed, the unnecessary parts of the conducting material which stick out from the through-hole 12 are removed by CMP (Chemical Mechanical Polishing). Then, a wiring layer 15 which becomes the wires and electrode pads is formed by patterning using copper (Cu) for example on the top and bottom surfaces of the silicon substrate 11.
However, in the through-hole electrode substrate 11 manufactured by the manufacturing method described above, a blow off phenomenon of the wiring layer 15 which occurs during an annealing process, or bumps or cracks which occur on the insulating film 13 within the through-hole 12, have been confirmed.
For example, Japan Laid Open Patent 2002-26520 and 2000-252599 propose methods for reducing the blow off phenomenon of the wiring layer and insulating layer bumps or cracks which occur during an annealing process in the manufacturing process of the through-hole electrode substrate described above. In the multilayer wiring substrate disclosed in Japan Laid Open Patent 2002-26520, an opening is arranged on a via island which is arranged directly above a via hole conductor which is filled with a conductive paste, and is formed so that it passes completely through the substrate, and expansion of a gas and water component which are included in the conductive paste is prevented during a heating process. In the print substrate which is disclosed in Japan Laid Open Patent 2000-252599, a hole which connects with the external atmosphere is arranged on a conducting film which covers the surface of a sealing member of a resin which is filled into a through-hole, and a gas which is discharged from the sealing member is discharged to the external atmosphere by heating during reflow.
However, the multilayer wiring substrate and printed circuit board proposed in Japan Laid Open Patent 2002-26520 and 2000-252599 apply to the defects which occur from the gas which is discharged from the through-hole electrode in which the through-hole is filled with a conductive paste or resin, and, as explained below, do not apply to defects which occur from the gas which is discharged from the through-hole electrode in which the through-hole is filled with a metal material forming an insulating layer.
FIG. 19 is a diagram which exemplifies the phenomenon whereby the wiring layer 15 is pushed up and the blow off phenomenon. In this case, a metal material such as copper (Cu) which is filled into the through-hole 12 as a through-hole electrode 14, is stretched, and by discharging the remaining gas (water (H2O) or hydrogen (H2) etc) in the metal material in the annealing process, the wiring layer 15 is pushed up and it is confirmed that the blow off phenomenon occurs. FIG. 21 is a diagram which shows a microscope photograph of a part in which the blow off phenomenon has occurred in one part of a plurality of electrode pads. FIG. 22 is a diagram which shows a microscope photograph of a part in which a swelling phenomenon in one part of the plurality of electrode pads, and mask swelling with regards to the electrode pads occurs.
FIG. 20 is a diagram which exemplifies the phenomenon by which cracks occur in the insulating layer 13. In this case, in the annealing process, when a heating temperature is more than 400° C. for example, bumps and crack occur in the insulating layer 13 due to the difference in the coefficient of thermal expansion between a metal material such as copper (Cu) which is filled as the through-hole electrode 14 and an insulation material such as SiO2 which is used as the insulating layer 13, the metal material enters into the cracks and there is a possibility of short circuits occurring between through-hole electrodes. FIG. 23 is a diagram which shows an SEM photograph of a part in which bumps occur in one part of the insulating layer 13. FIG. 24 is a diagram which shows an SEM photograph of a part in which cracks occur in one part of the insulating layer 13. To prevent this occurring, when performing an annealing process on the through-hole electrode substrate 10 it is necessary to set a low heating temperature. However, the annealing process is necessary and because the gas discharge from within the through-hole electrode 14 described above occurs even at a heating temperature at which cracks are not produced, measures are required.